Miniaturization of MOSFETs, which constitute the basis of silicon LSIs (Large Scale Integrated circuits), has been achieved heretofore along the fundamental concept of "Scaling Rule". For instance, 1-megabit chips of DRAM (Dynamic Random Access Memory), representative of the LSIs at present, are fabricated by use of FETs with a gate length of 1 .mu.m, whereas a gate length of 0.8 .mu.m is adopted for 4-megabit chips of DRAM, for which systems for mass production have been being put into order. It is certain that the size of semiconductor devices will be reduced further in company with the progress of miniaturization techniques.
The miniaturization of MOSFETs has been achieved not only by size reductions but by effective suppression of the punch-through phenomena which becomes stronger as size reduction proceeds. The achievement has been made with the aforementioned scaling rule as a guideline. According to the guiding principle, a reduction in size has been accomapnied by an increased substrate concentration, a thinner gate oxide film, and a shallower junction in source/drain regions. The principle should be maintained in making a further miniaturization of FETs. It is also true, however, that a variety of retardation factors in miniaturization have become clear. For example, the limit of thinning a gate oxide film is said to be 4 nm, because of the tunneling phenomea brought about directly by the thinning. Also, making a shallower junction is dependent on the diffusion of impurities, and it is impossible to achieve a junction depth of 0.05 .mu.m or below. In order to realize a shorter channel, therefore, substrate concentration must be increased. The increase of substrate concentration causes a threshould voltage rise, leading to worse performance such as increased junction capacitance and lowered junction breakdown voltage. For solving the problems, FET structures as shown in FIGS. 3 to 5 have been proposed. A characteristic feature common to these structures is the so-called elevated structure in which source/drain regions are raised above the substrate surface. Another common feature is that gate length is determined self-alignedly by the space defined by the elevated junctions. Therefore, with the lithography technique on the order of 0.5 .mu.m used for the recently started mass production of 16-megabit DRAMs, it is comparatively easy to realize a gate length of 0.3 .mu.m or below, though depending on the thickness of oxide film formed on the sidewall. Besides, because impurities for suppression of FET punch-through can be implanted through the space between the adjacent elevated junctions, excessive rise in substrate concentration is obviated. Accordingly, the increase in junction capacitance is smaller, as compared to the cases of FETs of conventional structures.
Respective features of the FET structures mentioned above will now be described briefly, with reference to the drawings. Referring to FIG. 3, there is shown a structure disclosed in Japanese Patent Laid-Open No. 62-35570. The structure is characterized in that the area of junction 11 in the source/drain region is determined self-alignedly. To achieve this, a process is adopted in which the formation of field isolation oxide 2 on a substrate 1 is followed by formation of a dummy gate (not shown), self-aligned formation of an oxide film on the sidewall of the dummy gate, and selective oxidation with the sidewall film as a mask to re-oxidize the substrate. As a result of the oxidation, an oxide film 30 which determines the source/drain regions is grown on the substrate, in addition to the field isolation oxide 2. Thus the area of the source/drain region can be reduced. However, the gate length is determined by the width of the dummy gate, so that the feature of self-aligned determination of gate length is lost. In FIG. 3, numeral 1 denotes a semiconductor substrate, 2 field isolation oxide, 4 an elevated junction, 5 an oxide film, 11 a junction in the substrate, 12 an oxide film covering the sidewall of the elevated junction, 13 a gate oxide film, 14 a gate electrode, and 30 and 31 each denote an oxide film.
FIG. 4 shows a structure disclosed in Japanese Patent Laid-Open No. 60-124874. The structure is characterized in that junction is formed by impurity diffusion from an oxide film. For this purpose, a composite film consisting of an oxide film 32 which contains impurities, an oxid film 5 which does not contain impurities, and polysilicon 4 is first deposited on a substrate. Next, a region for gate formation is opened, and a polysilicon film 8 is formed on the sidewall of the elevated junction. The polysilicon-coated sidewall is covered further with an oxide film, for insulation between the elevated junction and the gate electrode 14. In this case the oxide film is a two stories film, with impurities contained in the lower oxide 32 and diffused therefrom to form a portion of junction 11 in the substrate. This structure, unlike the structure of FIG. 3, eliminates the need for impurities to be diffused under the sidewall oxide film 12 from the elevated polysilicon, and can yield a comparatively shallow junction. However, the impurity diffusion from the oxide film is almost impossible unless a considerably large amount of impurities are contained in the oxide film. Moreover, where impurites are introduced into the oxide film by ion implantation or the like, the impurities rarely diffuse. In the figure, numeral I denotes a semiconductor substrate, 4 polysilicon, 5 an oxide film, 8 sidewall polysilicon, 12 a sidewall oxide film, 13 a gate oxide film, 14 a gate electrode, 15 an oxide film, 17 wiring, and 32 denotes an oxide film which contains inpurities.
FIG. 5 shows a structure disclosed in Japanese Patent Laid-Open No. 2-129928, in which controlled diffusion of impurities at source/drain edges is mentioned as one of the characteristic features of the structure. To achieve this, elevated polysilicon 4 is deposited on a substrate 1 provided with field isolation oxide 2, and the polysilicon 4 is processed into shape and then coated with an oxide film (not shown). Subsequently, a photo-resist is deposited so as to fill a gate-forming region, while leaving exposed the oxide film covering the sidewall of the polysilicon 4, and the sidewall oxide film is removed. As a result, a gap corresponding to the thickness of the oxide film is produced between the photo-resist filling the gate region and the elevated polysilicon 4. Impurites are implanted through the gap, whereby junction can be formed. According to this process, impurity distribution at source/drain edges can be controlled. The process, however, requires complicated procedures such as filling the gate region with photo-resist. According to the structure and fabrication process, in addition, it is difficult to produce FETs with different gate lengths, because of the need for filling the gate region. In the figure, numeral 1 denotes a semiconductor substrate, 2 field isolation oxide, 4 polysilicon, 5 an oxide film, 11 junction, 12 a sidewall oxide film, 13 a gate oxide film, and 14 denotes a gate electrode.
As has been described above, the elevated types of MOSFET as shown in FIGS. 3 to 5 have several advantageous features, over the MOSFET structures according to the prior art. The advantageous features can be summarized as follows: (1) gate length can be determined self-alignedly by the space between elevated source/drain regions and by the thickness of the oxide film on the sidewall of the elevated source/drain region; (2) there is a possibility that the area of the junction region may be determined self-alignedly; and (3) the resistance of source/drain junction can be lowered. Especially, in view of the fact that the smallest dimensions attainable with the current mass-production technology are on the order of 0.5 .mu.m and there are technical problems yet to be solved for realizing further smaller dimensions, the above feature (1) which enables more reductions in size with the current technology is an important factor for further progress of device miniaturization. Besides, in consideration of the above-mentioned need for further rise in substrate concentration, the increases of junction resistance and junction capacitance are inevitable according to the prior-art structures. In this point, the features (2) and (3) offer great advantages.
However, the elevated type MOSFETs have a very serious drawback as to production. The drawback is that the junction at source/drain edges cannot be controlled. In the structure shown in FIG. 3, for example, the junction 11 in the substrate is formed by diffusion from the polysilicon 4 elevated on the substrate. In the diffusion, the impurities must be diffused under the oxide film 12 covering the sidewall of the elevated polysilicon 4 to reach the source/drain edge. Diffusion depth is determined by the thickness of the sidewall oxide film 12, but the film thickness cannot be reduced greatly, from the viewpoints of breakdown voltage and capacitance with respect to the gate electrode. Consequently, the junction will be deep.
The structures shown in FIGS. 4 and 5 have been devised in order to overcome the above drawback. In the structure shown in FIG. 4, control of impurities at source/drain edges is by diffusion from the oxide film 32 which contains the impurities. For the structure of FIG. 5, on the other hand, control of the impurity distribution at source/drain edges by implantation through a gap has been contrived, as described above. However, the impurity diffusion from the oxide film is possible only where large amounts of impurities are preliminarily incorporated in the oxide film. Moreover, the desired diffusion is utterly impossible where the impurities have been introduced into the oxide film by ion implantation or the like. The structure shown in FIG. 5, in addition, requires a complicated and less reliable process which comprises, for example, once filling only the gate region with a photo-resist. According to the process, furthermore, the gate region is assumed to be filled with a photo-resist or the like, and it is difficult to fabricate FETs having different gate dimenions.